2017 恩智浦半导体校园招聘补招-研发类职位(上海/苏州)

东大小小



2017 恩智浦半导体校园招聘补招-研发类职位(上海/苏州)


 


About the company:NXP
Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and
infrastructure for a smarter world, advancing solutions that make lives easier,
better and safer. As the world leader in secure connectivity solutions for
embedded applications, NXP is driving innovation in the secure connected
vehicle, end-to-end security & privacy and smart connected solutions
markets. Built on more than 60 years of combined experience and expertise, the
company has 45,000 employees in more than 35 countries.


More information: www.nxp.com


 


How to apply:


Please send your CV our recruiters, specifying the position
you’re applying to.


Shanghai position: emily.qian@nxp.com


Suzhou position: fiona.chen@nxp.com


 


Hot job:


1.      Shanghai - IC Design Backend Engineer


2.      Shanghai - IC Design and
Verification Engineer


3.      Shanghai – DFT (Design for Test)
Engineer


4.      Suzhou - Digital Verification
Engineer


5.      Suzhou - Mix-Signal Verification
Engineer


6.      Suzhou - Analog/Mixed Signal Design
Engineer


 


Shanghai – IC Design
Backend Engineer


Send CV to emily.qian@nxp.com, specifying the position you’re applying to.


Responsibilities:


1.      Work with the global design team to do complex SOC physical
implementation for deep submicron design.


2.      Participates in block level backend design for complex SOC
designs.


3.      Responsible for RTL to GDS flow including CPF definition,
logic/physical synthesis, die size estimation, floor-planning, power planning,
CTS, place and route, STA, signal integrity, timing closure, formal
verification, DFM, DRC/LVS etc.


4.      Play a critical role in high performance design timing closure.


Requirements:


1.      University
degree in microelectronics engineering or equivalent, master degree or above is
preferred;


2.      2+ years
industry experience, at least 1 year in physical design role in submicron
projects;


3.      Good
understanding on backend flow and process;


4.      Successful completion of 2+ physical design projects (at least one
at 65nm or below);


5.      Experience on Cadence, Synopsys, Magma, Mentor tools;


6.      Hands on
experience on floorplan, place and route, STA, DRC/LVS;


7.      Hands on
experience on synthesis, IR drop and signal integrity is preferred;


8.      Good
communication skills is must, English language proficiency.


 


Shanghai - IC Design and Verification
Engineer


Send CV to emily.qian@nxp.com, specifying the position you’re applying to.


 


Responsibilities:


1.      Design and develop digital circuits for ARM core based SOC
projects and IPs.


2.      Verification in module level and chip level, define and execute
verification plan with full functional coverage. 


3.      Involved in the SoC level and Digital IP design and verification,
and the SoC development for ARM based SoC projects.


4.      Do RTL coding, integration and verification.


5.      Do simulation in gate level, transistor level (full-chip spice).


6.      Create function test patterns for testing engineering.


Requirements:


1.      Bachelor or master degree in Microelectronics, Electronics,
Electrical Engineering, Computer Science or relevant disciplines.


2.      Good knowledge and have experience in digital circuit
design/verification with Verilog/VHDL.


3.      Can use the EDA tools from Cadence, Synopsys, or Mentor tools for
digital and/or analog developing.


4.      Have knowledge about computer architecture, 8bit, 16bit or 32bit
Micro-controller or Micro-processer is a plus.


5.      Have knowledge on AMBA bus system is a plus.


6.      Knowledge and experiences on verification and verification
methodology is a plus.


7.      Good language skill in English. Passed CET-6.


8.      Have basic knowledge of VLSI design flow.


 


Shanghai – DFT
(Design for Test) Engineer


Send CV to emily.qian@nxp.com, specifying the position you’re applying to.


 


Responsibilities:


1.      Design and integration DFT logic including SCAN, MBIST, JTAG,
Boudary Scan etc


2.      DFT strategy definition and implementation


3.      Generate patterns for ATE and pattern support


4.      Responsible for DFT related STA check or SDC delivery


5.      Support silicon bringup


Requirements:


1.      University
degree in microelectronics engineering or equivalent, master degree or above is
preferred;


2.      2+ years
industry experience, at least 1 year in physical design role in submicron
projects;


3.      Good
understanding on backend flow and process;


4.      Successful
completion of 2+ physical design projects (at least one at 65nm or below);


5.      Experience
on Cadence, Synopsys, Magma, Mentor tools;


6.      Hands on
experience on floorplan, place and route, STA, DRC/LVS;


7.      Hands on
experience on synthesis, IR drop and signal integrity is preferred;


8.      Good
communication skills is must, English language proficiency.


 


Suzhou - Digital Verification Engineer


Send CV to fiona.chen@nxp.com, specifying the position you’re applying to.


 


Responsibilities:


1.      Main responsible on IP level, subsystem level and SoC level
verification for connectivity MCU, MPU which targets IoT application. the
verification work includes develop test benches, modeling,
assertions/checkers/monitors, test plan and test development and sign off for
tape out.


2.      Support the IP and SoC design, architecture definition. 


3.      Join the verification methodology innovation.


Requirements:


1.      Bachelor or master degree, majoring in microelectronics,
electronic engineering , computer science or relevant disciplines.


2.      Good language skill in English, passed CET-6.


3.      Have knowledge about EDA simulation and synthesis tool as well as
VLSI design flow.


4.      Good knowledge in Verilog, VHDL, System Verilog, and script
language.


5.      Good knowledge in RTL code style, full synchronous design style,
and knowledge of Design-for-Test (DFT) is a plus.


6.      Complex IP/ SOC Design Verification, direct experience in IP/SOC
or Wireless MAC/Tranceiver (BLE, Zigbee,Wi-Fi,NFC),or Industry bus standard
(PCI-e, USB) is preferred.


7.      Have used Unix/Linux system and EDA tool from Cadence, Synopsis,
Mentor digital and/or analog development. 


8.      Have knowledge about computer architecture, 8bit, 16bit or 32bit
Micro-controller or Micro-processer is a plus.


9.      Have knowledge of OVM,VMM or UVM is a plus.


10.   Have knowledge of Wireless communication ,DSP is a plus.


11.   Prefer know-how of ARM or AHB bus system.


12.   Prefer experience of formal verification with property scheme, for
example SVA (System Verilog Assertion).


 


Suzhou - Mix-Signal Verification Engineer


Send CV to fiona.chen@nxp.com, specifying the position you’re applying to.


 


Responsibilities:


1.      Main responsible on IP level, subsystem level and SoC level
verification for connectivity MCU, MPU which targets IoT application. Define
and execute verification plan with full functional coverage. 


2.      Support the IP and SoC design, architecture definition.


3.      Work on mixed signal simualtion on IP level,Sub- system level and
SoC level.


4.      Work on transistor level spice simulation for the SoC.


5.      Join mix-signal verification methodology innovation.


Requirements:


1.      Bachelor or master degree, majoring in microeletronics, electronic
engineering , computer science or relevant disciplines.


2.      Good language skill in English, passed CET-6.


3.      Have knowledge about EDA simulation and synthesis tool as well as
VLSI design flow.


4.      Basic knowledge in Verilog, VHDL, System Verilog,  and script language.


5.      Basic knowledge of analog design and transistor level simulation.


6.      Have used Unix/Linux system and EDA tool from Cadence, Synopsis,
Mentor digital and/or analog development. 


7.      Have knowledge about computer architecture, 8bit, 16bit or 32bit
Micro-controller or Micro-processer is a plus.


8.      Prefer know-how of ARM or AHB bus system.


9.      Have knowledge of analog and mixed signal simulation is a plus.


10.   Have knowledge of Analog RF is a plus


 


Suzhou - Analog/Mixed Signal Design
Engineer


Send CV to fiona.chen@nxp.com, specifying the position you’re applying to.


 


Responsibilities:


1.      Responsible for analog / mixed-signal IP  design for MCU product development


2.      Independent IP schematic design / analog & mix-signal
simulation/ layout design / IP view generation / technical documentation


3.      Work with SoC / Backend team on IP integration.


4.      Work with test/validation/qualification team on IP validation,
characterizations and failure analysis.


Requirements:


1.      Master Degree in Electrical or Computer Engineering.


2.      Familiar with analog/mix-signal IC schematic and layout design


3.      Familiar with design EDA tool: Hspice/Spectre,  Virtuso,  Calibre, Assura, QRC;


4.      Familiar with lab equipments and  silicon validation /debug flow


5.      Experience in power management module design ( high accuracy
bandgap /LDO/DC-DC/…) is a plus


6.      Experience in data conversion module design ( ADC/DAC) is a plus


7.      Experience in clock generation module design ( crystal osc/
relaxation osc/ /PLL/FLL/..) is a plus


8.      Experience with mix-signal circuit modeling & simulation is a
plus


9.      Good communication skills and team work


10.   Good oral and written English skills


 



——十年了,已经十年了,我还以为国家根本把我忘记了——怎么会呢,就算是一条内裤,一张卫生纸,都有它的用处!